1. Field of the Invention
The present invention generally relates to semiconductor devices and manufacturing methods of the same, and more specifically, to a semiconductor device having a PBGA (Plastic Ball Grid Array) package structure and a manufacturing method of the semiconductor device.
2. Description of the Related Art
As today's electronic apparatuses have miniaturized sizes, high functionalities or high densities, it is required that electronic parts such as semiconductor devices applied to the electronic apparatuses also have miniaturized sizes or be thin. Because of this, as a package proper for high density mounting wherein a mounting area is reduced by miniaturization, a surface mount technology type package such as a PBGA (Plastic Ball Grid Array) has been suggested.
FIG. 1 is a view showing a structure of a related art semiconductor device having the PBGA (Plastic Ball Grid Array) package. More specifically, FIG. 1(b) is a cross-sectional view taken along line X-X′ of FIG. 1(a).
Referring to FIG. 1, a related art semiconductor device 10 having the PBGA package has a structure where a semiconductor device 2 is mounted on a wiring board 1 via a die bonding member not shown in FIG. 1, such as a die bonding film.
The semiconductor element 2 is connected to the wiring board 1 by bonding wires 3 made of gold (Au) or the like.
A basic material of the wiring board 1 is insulation resin such as glass-epoxy resin. On an upper surface of the wiring board 1, a conductive layer 4A made of copper (Cu) or the like is selectively provided. The conductive layer 4A other than areas where the bonding wires 3 are connected is selectively covered with a resist layer 5A.
In addition, on a lower surface of the wiring board 1, a conductive layer 4B made of copper (Cu) or the like is selectively provided. The conductive layer 4B is selectively covered with a resist layer 5B. Plural outside connection terminals (bumps) 6 such as spherical shape electrode terminals whose main ingredient is solder are arranged in a grid state on the conductive layer 6B defined by the resist layer 5B. The conductive layer 4B is connected to the conductive layer 4A.
The semiconductor element 2 and the bonding wire 3 are sealed by sealing resin 7 such as epoxy group resin.
However, the sealing resin 7 is not provided in the vicinities of both end parts of the wiring board 1. Therefore, the wiring board 1 projects to outside of the sealing resin 7.
A wiring pattern 9 formed on an upper surface of the wiring board 1 shown in FIG. 1(a) is made of copper (Cu). Nickel gold (Ni—Au) plating is applied on a surface of the wiring pattern 9. The wiring pattern 9 functions as a flow path of the molten sealing resin 7 when the sealing resin 7 is provided on the wiring board 1 by using a mold based on a transfer molding method. Since adhesion of the Nickel gold (Ni—Au) plating to the sealing resin 7 is not good, it is possible to easily remove a runner.
Equipment used for manufacturing a related art lead frame type package can be applied to manufacturing the semiconductor device 10 having such a PBGA package structure. This is discussed with reference to FIG. 2.
Here, FIG. 2 is a plan view showing a relationship between the related art semiconductor device 10 having the PBGA package structure shown in FIG. 1 and a related art lead frame type semiconductor device. The related art semiconductor device 10 having the PBGA package structure shown in FIG. 1 is shown at the right side of FIG. 2, and the related art lead frame type semiconductor device 20 is shown at the left side of FIG. 2.
In the lead frame type semiconductor device 20, a semiconductor element provided on a die pad is connected to inner leads by bonding wires. The inner leads, the semiconductor element provided on the die pad, and the bonding wires are sealed by sealing resin 21. Outer leads 22 are extended from the inner leads to outside of the sealing resin 21.
As shown by the dotted areas in FIG. 2, configuration or package size of the semiconductor device 10 having the PBGA package structure shown in FIG. 1, namely configuration or size of the sealing resin 7, is substantially the same as configuration or package size of the lead frame type semiconductor device 20, namely configuration or size of the sealing resin 21.
Accordingly, the equipment used for manufacturing the related art lead frame type semiconductor device 20 can be applied to manufacturing the semiconductor device 10 having the PBGA package structure, so that a limitation of having a large number of pins in the lead frame type semiconductor device 20 can be solved.
Japanese Patent No. 3534501 discloses a semiconductor device provided by arranging a semiconductor pellet on a top plane of a substrate with plural connecting terminals. In this semiconductor device, a group of the connecting terminals is arranged in plural annular lines at the periphery of the semiconductor pellet. A space with a low height formed between the semiconductor pellet and the substrate by the connecting terminal group is filled with resin so that a reinforcing resin layer is formed.
In addition, Japanese Patent No. 3565204 discloses an electronic apparatus having the following structure. The electronic apparatus comprises an element mounting substrate having an electrode formed on the rear side of an element mounting surface, a wiring board which is arranged so as to face the element mounting substrate across a prescribed interval and which has an electrode formed at a position facing the electrode of the element mounting substrate, a meltable member for joining the electrode of the element mounting substrate with the electrode of the wiring board, and a resin reinforcing member which is arranged outboard of the meltable member for joining the end of the element mounting substrate with the site of a wiring substrate facing this end.
However, the semiconductor device 10 having the PBGA package structure shown in FIG. 1 has a problem shown in FIG. 3. Here, FIG. 3 is an enlarged view of a part surrounded by a dotted line in FIG. 1.
As discussed above, the configuration or package size of the semiconductor device 10 having the PBGA package structure shown in FIG. 1, namely the configuration or size of the sealing resin 7, is substantially the same as the configuration or size of the package of the lead frame type semiconductor device 20, namely the configuration or size of the sealing resin 21. In addition, as discussed with reference to FIG. 1, the sealing resin 7 is not provided in the vicinities of both end parts of the wiring board 1. Only the wiring board 1 projects to the outside of the sealing resin 7.
However, coefficients of thermal expansion of members forming the semiconductor device 10 shown in FIG. 1 are different from each other. For example, the coefficient of thermal expansion of silicon (Si) used as the semiconductor element 2 is 3×10−6/° C., the coefficient of thermal expansion of the sealing resin 7 is 8×10−6/° C., and the coefficient of thermal expansion of the wiring board 1 is 16×10−6/° C.
In addition, for example, the temperature inside of a reflow hearth in a reflow process for mounting a package on the wiring board 1 reaches around 260° C. Heat is applied as a reliability test of the semiconductor device 10. Furthermore, in normal use of the semiconductor device 10, the semiconductor device 10 may be put under atmospheric conditions wherein the temperature in summer may be higher than 80° C.
Accordingly, under the atmospheric conditions wherein such a temperature change occurs, the members may expand or contract, due to the difference of the coefficients of thermal expansion of the members, concentration of stress may be generated at a boundary part of an end part of the sealing resin 7 and the wiring board 1.
In addition, in a process of manufacturing the semiconductor device 10, for example, bending when the external configuration is formed by using a dicing blade or the like or concentration of mechanical stress due to a fall of the semiconductor device 10 or the like may be generated at the boundary part of an end part of the sealing resin 7 and the wiring board 1.
Due to such concentration of stress, as shown in FIG. 3, a crack (indicated by “X” in FIG. 3) is generated in the wiring board 1 so that bad conductivity, namely pattern breakage, of the conductive layer 4 of the wiring board 1 is caused. As a result of this, an electric property of the semiconductor device may be degraded.